OUR MISSION:
Re-thinking sparse math in silicon

SparXiom is a UK-based fabless semiconductor IP startup company engineering the next generation of sparse compute architectures. We want to solve the industry's most critical hardware bottleneck: achieving maximum theoretical saturation of SIMD vector and 2D systolic arrays on highly irregular, unstructured sparse data—whilst addressing compute domains ranging from large-scale scientific High-Performance Computing (HPC) to Edge AI and real-time LLM autoregressive token decoding.

Our technology is built upon the (unpublished) proprietary SpAx data format and related sparse streaming 'family of algorithms': our hardware-software co-design allows rigid vector and systolic array compute units to process unpredictable SpMV, SpMM, and SpGEMM workloads with near-O(1) efficiency.

The potential is not just theoretical. Software emulation on Tier-0 supercomputer (Intel Sapphire Rapids AVX-512 and AMX nodes) demonstrates that, in certain sparsity regimes, our streaming algorithms can already match and outperform Intel’s oneMKL library on bare metal.

These validated cycle-accurate gold models serve as the foundational blueprints for our future core licensable silicon products: the Sparse Streaming Coprocessor (SSC) and the Sparse Tiling Coprocessor (STC). The main hypothesis is that significant increases in speed and performance-per-watt can be achieved over incumbent general-purpose architectures by implementing SpAx execution models as microcode in these host-agnostic IP blocks.

SparXiom is currently operating in stealth mode (working on FPGA prototype of SSC and patent development), and actively seeking engagement with lead investors possessing deep semiconductor expertise to join us and accelerate hardware development and commercialisation.